This invention relates to automated test equipment for testing integrated electronic circuits, and more particularly to correcting for pulse width timing errors in such equipment.
Automated test equipment (ATE) is used for testing (e.g., in a semiconductor chip fabrication facility) to simulate the operating conditions that an integrated circuit (chip) will experience when used in the field. An integrated circuit undergoing testing is also known as a device under test (DUT).
The ATE is controlled by an associated computer or processor which executes a set of instructions (the test program). The ATE must supply signals having the correct voltages, currents, timings and functional states to the DUT and monitor the responses from the DUT. The ATE then compares the responses from each test to pre-defined limits and a pass/fail decision is made.
A test xe2x80x9ceventxe2x80x9d is a pair expressed as the notation (S, T) where xe2x80x9cSxe2x80x9d is a functional state and xe2x80x9cTxe2x80x9d is the time associated with the transition to S. An xe2x80x9cevent sequencexe2x80x9d is a time-ordered list of such pairs. For example, in the signal waveform shown in FIG. 1, the event sequence has four events expressed as (D1, 3), (D0, 7), (D1,10), and (D0, 14). The first event drives the signal to a high state (1) at time=3 nanoseconds (ns). The second event drives the signal to a low state (0) at time=7 ns. The third event drives to a high at time=10 ns and the fourth event drives to a low at time=14 ns. (xe2x80x9cAmplitudexe2x80x9d in FIG. 1 is a signal voltage which is set by the test program.)
The first two events can be said to describe a pulse 101xe2x80x94a transient signal that is of short duration, and one polarity. The pulse has a leading edge 103 and a trailing edge 105. The pulse width, or pulse duration, is the time interval between points on the leading and trailing edges at a specific voltage value, usually the time interval between the half amplitude points of the pulse. Thus, the pulse width of pulse 101 is about 4 nanoseconds (ns). Similarly, the pulse width of pulse 107 is about 4 ns.
ATE signals are affected by many error sources, but among the most significant in high performance testers is an error related to pulse width, as shown in FIG. 2. As the intended (nominal) pulse width becomes smaller, it becomes less likely that the pulse will reach full amplitude before it is instructed by the tester to reverse itself. Therefore, the trailing edge of the pulse occurs earlier than desired. The actual pulse width is less than the nominal pulse width, and a timing error results. Line 205 depicts the error curve, which indicates that the timing error increases as nominal pulse width decreases. The error curve could be more erratic, as shown in line 207. As long as the error curve is predictable, however, pulse width timing error could be accounted for. A pulse width timing error has been found to occur on a particular tester when the pulse width is decreased to 1.25 ns or less. Thus, the second of two timing edges that are intended to be 1 ns apart will have a timing error if and only if the following 3 conditions are satisfied: 1) 1 ns is sufficiently small to cause the small pulse error for the circuit; 2) the first edge actually caused a transition in the state of functional data; and 3) the second edge is of opposite polarity from the first.
Conditions 2) and 3) above imply that there can be no pulse width (and hence no small pulse width timing error) unless there is a transition in functional states being sent from the driver circuit of the tester to a terminal of the DUT. Accordingly, pulse width error is a function of the functional data stream arriving at the terminal of the DUT. Consider, for example, a sequence of functional data (F1-F8) xe2x80x9c01111010xe2x80x9d, each datum being instructed by the tester to occur in this order at 1 ns intervals on a terminal of the DUT. The waveform corresponding to this sequence of functional data is shown in FIG. 3. In this case, datum F5 does not cause a transition, so has no pulse width. F6 causes a transition from 1 to 0 and has a pulse width of 4 ns. F7 causes a transition from 0 to 1 and has a pulse width of 1 ns. F8 causes a transition from 1 to 0 and has a pulse width of 1 ns. There is no pulse width timing error associated with F5, because there is no transition in functional state. There is no significant pulse width timing error associated with F6, because, though there is a transition in functional state, the pulse width here is 4 ns, which is greater than the critical value of 1.25 ns. F6 is said to be ending a pulse, but not a xe2x80x9cshortxe2x80x9d pulse (a pulse is herein termed a xe2x80x9cshortxe2x80x9d pulse if it is 1.25 ns or less in duration). There is a pulse width timing error associated with F7, because it causes a transition in functional state, and has a pulse width of 1 ns. F7 is said to be ending a short pulse. Similarly, there is a pulse width timing error associated with F8, because (like F7) it causes a transition in functional state and has a pulse width of 1 ns. Thus, F8 is also said to be ending a short pulse. This pulse width timing error has been found to be on the order of 30 picoseconds (ps), when the functional data occurs at 1 ns intervals. Pulse width error increases with the frequency of functional data output. For example, when the functional data occurs at 800 ps intervals, the pulse width error grows to 50 ps. As mentioned above, a pulse width timing error has been found to occur on a particular tester when the pulse width is decreased to 1.25 ns or less. Thus, to determine whether the second of two timing edges (represented by a bit of functional data) that are programmed to be 1 ns apart has a pulse width timing error, the bit of functional data must be analyzed in view of the two bits that precede it. For example, F2, F3, and F4 are required to determine the pulse width prior to F4.
There is a need to be able to correct for this pulse width timing error, especially during testing of high performance integrated circuits. For example, the very high frequency of RAMBUS 64/72 Mbit DRAM (dynamic random access memory conforming to the RAMBUS standard) demands extremely accurate testers to successfully test the devices; a timing edge placement accuracy (EPA) of +/xe2x88x9250 picoseconds (ps) is required. Presently, no solution has been put forward to solve this problem.
The present invention is directed to methods of and apparatus for correcting for pulse width timing errors as described above. According to the current art, a test program first loads scrambler and sequencer memories (each terminal of a DUT having associated with it one of each of these memories) with information representing event timing values and event type data for the events that are to occur during a test vector, (as in the well known Schlumberger Sequencer Per Pin(copyright) architecture).
A method for correcting for pulse width timing error during testing of an integrated circuit is described. The method includes storing in a memory, associated with a selected terminal of an integrated circuit, event timing data pertaining to testing of the integrated circuit. Functional data is provided, pertaining to the testing, and it is determined if the functional data causes a state transition in the integrated circuit, the state transition causing a pulse. If a pulse is created, then the event timing data is adjusted, thereby to produce pulse width adjusted event timing. A test signal is then applied to the selected terminal of the integrated circuit, the test signal including pulse width adjusted event timing.
Two apparata for implementing the method of the present invention are herein described. One apparatus implements single value pulse width calibration. In one embodiment of this apparatus, the elements include a decoder, a source of functional data having an output terminal coupled to the decoder, and also having a second output terminal. Also included is an event sequencer, having a first set of storage locations associated with a selected terminal of the integrated circuit, and storing event timing data and event type data. The event timing data includes nominal event timing and pulse width adjusted event timing. Logic circuitry have an input terminal coupled to the output terminal of the source of functional data, and further have an output terminal. The apparatus further includes a second set of storage locations, associated with the selected terminal of the integrated circuit. The second set of set of storage locations has an input terminal coupled to the output terminal of the logic circuitry and at least one output terminal coupled to an input terminal of the first set of storage locations, the second set of storage locations storing different addressing data for the first set of storage locations. The decoder has a first input terminal coupled to receive the event timing and event type data from the first set of storage locations and a second input terminal coupled to the output terminal of the source of functional data.
According to one embodiment of the present invention, also described herein as single value pulse width calibration, additional event timing values are provided that compensate for anticipated pulse width timing errors. The additional event timing values are produced by adding a calibration factor to the nominal timing values specified by the user. Since the magnitude of pulse width timing error is a function of pulse width (duration in time), a unique calibration factor is applied for a given pulse width. Also, additional scrambler memory locations are loaded with pointers to the appropriate adjusted event timing values.
During the functional test, a series of logic gates external to the local event sequencer of the tester analyzes the stream of functional data describing event polarity during every test cycle. In one embodiment, 8 bits of functional data are provided during every test cycle; four different series of logic gates analyze 2 bits of functional data each. The logic gates determine if a given bit of functional data causes a data state transition such that it ends a xe2x80x9cshortxe2x80x9d pulse, that is, a pulse whose width is small enough to require correction. The results of this analysis are expressed in binary form and become part of the address into the scrambler memory. The data stored at a particular scrambler memory address act as a pointer to select the location in the sequencer memory that contains the correct pulse width adjusted event timing data. Then, as in the prior art, an event type decoder combines the functional data values (supplied from a pattern data source, e.g., local memory or an algorithmic pattern generator of the tester) with the event time and event type data from the sequencer memory, provides further event timing calibration (to compensate for other factors affecting event timing) and provides an output signal to a second circuit. This second circuit converts the event time (now corrected for pulse width timing error), event type, and functional data to a corresponding event signal. The event signal is then transmitted to a driver circuit at the test head of the tester. (The DUT conventionally fits into a socket on top of a load board, which is on top of the test head). The driver circuit, in turn, changes the amplitude of the signal according to the user""s requirements, and applies the signal to a particular input terminal of the DUT. The receipt of the output signals in response and their analysis is conventional.
A second apparatus implements general pulse width calibration. In one embodiment of this apparatus, the elements include a decoder, a source of functional data having an output terminal coupled to the decoder, and also having a second output terminal. Also included is an event sequencer, having a first set of storage locations associated with a selected terminal of the integrated circuit, and storing event timing data and event type data. The event timing data includes nominal event timing only. The decoder has a first input terminal coupled to receive event timing and event type data from the first set of storage locations and a second input terminal coupled to the output terminal of the source of functional data. The apparatus further includes a second set of storage locations, associated with the selected terminal of the integrated circuit. The second set of set of storage locations has an output terminal coupled to an input terminal of the first set of storage locations, the second set of storage locations storing different addressing data for the first set of storage locations. Circuitry is coupled to an output terminal of the second set of storage locations and an output terminal of the decoder. The circuitry stores event timing and event type data for recent events, and calculates a pulse width of a present event, the circuitry further having an output terminal. A lookup table is coupled to the output terminal of the circuitry, and outputs at its output port a calibration factor, thereby outputting pulse width adjusted event timing.
According to a second embodiment of the present invention, also described herein as general pulse width calibration, pulse width calculation circuitry is included in the event sequencer which maintains a history of the recent events, and calculates the pulse width of the present event by subtracting the nominal time value for the most recent event of the opposite polarity from the nominal time value of the present event. The calculated pulse width value serves as an address into a lookup table, which provides a corresponding calibration factor to be added to the event timing value to correct for its pulse width error.